The present embodiments relate to forming integrated circuits and are more particularly directed to a performance and area scalable cell architecture technology.
The history and prevalence of integrated circuits are well known and have drastically impacted numerous electronic devices. As a result and for the foreseeable future, successful designers constantly are improving integrated circuit design, and improvements are in numerous areas including device performance and size. In general, integrated circuit design may be viewed in two steps, the first being electrical function and the second being physical layout. The latter attribute is the focus of the preferred embodiments and, thus, is further introduced below.
As further detailed later in this document, the physical layout of an integrated circuit is typically designed from layouts of smaller blocks. The smaller blocks are sometimes referred to as cells (or standard cells), and in this regard often designers establish different cells where each such cell has an associated functionality and layout. For example, the functionality may be to perform a logical function, such an inverter or other Boolean operation, including AND, NAND, OR, NOR, XOR, and XNOR, or the functionality may provide a storage function. Moreover, in some cases different cell layouts exist for the same functionality, where often the choice among those cells may be based on other either local or global circuit considerations, such as performance, speed, and power consumption. Thus, to design a portion of an integrated circuit or the entire circuit, an area is defined that will be physically located on the circuit, and cells for that area are chosen from a collection of different cells, typically referred to as a cell library (or plural, libraries). Each cell is selected from the library and located in different sub-areas within that area. In contemporary applications, these selections are performed by one or more processors operating in response to specialized software and data. In this regard, the software places the cells in locations along rows, where therefore the area or entire integrated circuit layout ultimately will include a very large number of such rows with cells aligned along each such row. Typically after the location of each cell is established, then routing is accomplished wherein interconnections are defined so as to connect various nodes of cell devices together.
In the context of cell libraries, the prior art includes various different cells. Among these cells are two different cells, shown in FIGS. 1 and 2, respectively, for implementing a pair of complementary MOS transistors, that is, where one transistor is NMOS (i.e., an n-channel MOSFET) and the other transistor is PMOS (i.e., a p-channel MOSFET). Each of these cells is described below.
Looking to FIG. 1, it illustrates a plan view of a prior art transistor cell TC1, having an NMOS transistor N1 and a PMOS transistor P1. These two transistors form a cell that is referred to as a single row cell because the cell has a boundary B1 that spans across one row when boundary B1 is aligned between two successive row boundary lines RB1 and RB2, where row boundary lines RB1 and RB2 are imaginary lines used for alignment of cell TC1 relative to other cells (not shown) in a physical circuit layout. NMOS transistor N1 includes a first and second N-type source/drain region S/DN1a and S/DN1b that are typically co-planar and diffused within a semiconductor substrate or region that is not perceptible from the perspective of FIG. 1, where the descriptor “source/drain” is used in this document to describe generically a region that may function either as a transistor source or a transistor drain, depending on connectivity to the transistor and so that when no such connectivity is illustrated, such a region could be either a source or a drain and, hence, is referred to as a source/drain. Further, NMOS transistor N1 includes a gate region GN1 formed above and between source/drain regions S/DN1a and S/DN1b that (although the source/drain regions may, in some approaches, extend to some extent under the gate region, with various descriptions for such an approach such as extended drain or low doped drain). PMOS transistor P1 includes a first and second P-type source/drain region S/DP1a and S/DP1b that are formed within an N-type well NW1 (or N-well), where N-well NW1 is also formed in the above-mentioned semiconductor substrate or region that is not perceptible from the perspective of FIG. 1. PMOS transistor P1 also includes a gate region GP1 formed above and between source/drain regions S/DP1a and S/DP1b (although the source/drain regions may, in some approaches, also extend to some extent under the gate region).
Looking to FIG. 2, it illustrates a plan view of a prior art transistor cell TC2, having an NMOS transistor that is created in two different and non-continuous areas, which for sake of this document and reference may be referred to as half transistors in that ultimately they are connected by interconnect (not shown) so that the respective gate and source/drain regions from each half transistor are electrically connected to one another to provide a single operational NMOS transistor. For sake of reference, therefore, one NMOS half transistor N2.1 is shown at the bottom of cell TC2 and another NMOS half transistor N2.2 is shown at the top of cell TC2. Moreover, cell TC2 also includes a PMOS transistor P2. Thus, for cell TC2, PMOS transistor P2 and the entirety of the NMOS transistor that is formed by half transistors N2.1 and N2.2 form a cell that is referred to as a double row cell because the cell has a boundary B2 that aligns on its ends along boundary row lines and spans across two adjacent rows, as defined between a row boundary line RB1, across a next successive row boundary line RB2, and then reaching another row boundary line RB3, where again the row lines are imaginary lines used for alignment of cell TC2 relative to other cells (not shown) along the same rows in a physical circuit layout. NMOS half transistor N2.1 includes a first and second N-type source/drain region S/DN2.1a and S/DN2.1b that are typically co-planar and diffused within a semiconductor substrate or region that is not perceptible from the perspective of FIG. 2, and a gate region GN2.1 is formed above and between source/drain regions S/DN2.1a and S/DN2.1b (where again the source/drain regions may, in some approaches, extend to some extent under the gate region). Similarly, NMOS half transistor N2.2 includes, physically removed from NMOS half transistor N2.1, a first and second N-type source/drain region S/DN2.2a and S/DN2.2b that are typically co-planar and diffused within the above-mentioned semiconductor substrate or region, and a gate region GN2.2 is formed above and between source/drain regions S/DN2.2a and S/DN2.2b. Note, therefore, that the overall source or drain regions of NMOS transistor N2 are in effect interrupted, that is, along their width (i.e., parallel to the length of their respective gate regions GN2.1 or GN2.2) they do not provide a continuous diffused source or continuous diffused drain region as is implemented for NMOS transistor N1 in transistor cell TC1, but instead the diffused or planar width of the source or drain is separated into two different regions; in other words, assume for sake of reference that source/drain region S/DN2.la is connected as a source in a given architecture, and likewise source/drain region S/DN2.2a is connected as a source in the given architecture; thus, the entirety of the combined widths of these two co-planar sources operate as a source for an NMOS transistor, but those two co-planar source regions are not continuous but instead separated physically from one another in the substrate (or well) into which they are formed. As a result, there is a loss of performance. Continuing with transistor cell TC2, PMOS transistor P2 includes a first and second P-type source/drain region S/DP2a and S/DP2b that are formed within an N-well NW2, where N-well NW2 is also formed in the above-mentioned semiconductor substrate or region. PMOS transistor P2 also includes a gate region Gp2 formed above and between source/drain region S/DP2a and S/DP2b.
Transistor cells TC1 and TC2 provide advantageous operation in various circuit applications. The art recognizes, however, that the choice between these cells involves tradeoffs. Specifically, transistor cell TC1 is smaller and therefore consumes less area on the integrated circuit die as compared to transistor cell TC2, where lower space usage is often important. Conversely, transistor cell TC2 operates faster that transistor cell TC1, and this faster speed is often desirable. Accordingly, this tradeoff also must be considered in circuit design and the prior art thereby provides drawbacks in its limitations of available cells with these tradeoffs. Against this background, the preferred embodiments include an additional cell layout that may be combined with the preceding cells and still others to provide further alternatives and additional performance benefits in some applications, as is appreciated from the remainder of this document.